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MYSON-CENTURY TECHNOLOGY
MTV412M (Rev 0.9)
8051 Embedded Monitor Controller 128K Flash Type with ISP
FEATURES
* * * * * * * * * * * * * *
8051 core, 12MHz operating frequency with double CPU clock option 0.35um process; 3.3V/5V power supply; 5V I/O tolerant 1024-byte RAM; 128K-byte program Flash-ROM support In System Programming (ISP) without boot code Maximum 14 channels of PWM DAC Maximum 38 (44-pin) or 36 (42-pin) I/O pins SYNC processor for composite separation/insertion, H/V polarity/frequency check and polarity adjustment Clock output to drive other devices Built-in low power reset circuit Compliant with VESA DDC1/2B/2Bi/2B+ standard Triple slave IIC addresses; two H/W auto transfer DDC1/DDC2x data for both D-sub and DVI interfaces Single master IIC interface for internal device communication Maximum 4-channel 8-bit A/D converter Flash-ROM program code protection selection 42-pin SDIP or 44-pin PLCC/PQFP package
GENERAL DESCRIPTIONS
The MTV412M micro-controller is an 8051 CPU core embedded device targeted for LCD Monitor, LCD TV or smart panel applications. It includes an 8051 CPU core, 1024-byte SRAM, on-chip 16K-bit EEPROM, 14 PWM DACs, VESA DDC for both D-sub and DVI interfaces, 4-channel 8-bit ADC, hardware ISP without boot code and a 128K-byte internal program Flash-ROM in 42-pin SDIP, 44-pin PLCC/PQFP package.
P1.0-7 P3.0-2 P3.4
P0.0-7 P2.0-3 RD WR ALE INT1
P0.0-7 P2.0-3 RD WR ALE INT1
XFR
AUXRAM & DDCRAM1 & DDCRAM2
8051 CORE
RST X1 X2 CKO
ADC
AD0-3
H/VSYNC CONTROL
HSYNC VSYNC HBLANK VBLANK HCLAMP VCOAST ISCL ISDA HSCL1 HSDA1 HSCL2 HSDA2
PWM DAC
P7.0-7 P6.0-7 P5.0-6 P4.0-2 DA0-13
AUX I/O
16K-BIT EEPROM
DDC & IIC INTERFACE
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
Revision 0.9
-1-
April 2002
MYSON-CENTURY TECHNOLOGY
PIN CONNECTION
MTV412M (Rev 0.9)
DA2/P5.2 DA1/P5.1 DA0/P5.0 VDD3 HSDA2/P7.6 HSCL2/P7.5 RST VDD VSS X2 X1 ISDA/P3.4/T0 ISCL/P7.7 P4.2 P6.2/AD2 P1.0 P1.1 P3.2/INT0 P1.2 P1.3 P1.4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36
VSYNC/P7.4 HSYNC/P7.3 DA3/P5.3 DA4/P5.4 DA5/P5.5 DA8/P7.1 DA9/P7.2 HBLANK/P4.1 VBLANK/P4.0 DA7/P7.0/HCLAMP DA6/P5.6/CKO P6.6/DA12 P6.5/DA11 P6.4/DA10 HSCL1/P3.0/Rxd HSDA1/P3.1/Txd P6.0/AD0 P6.1/AD1 P1.7 P1.6 P1.5
MTV412M 42 Pin SDIP
35 34 33 32 31 30 29 28 27 26 25 24 23 22
DA4/P5.4 DA3/P5.3 HSYNC/P7.3
VSYNC/P7.4 DA2/P5.2 DA1/P5.1
HSCL2/P7.5 RST VDD P6.3/AD3 VSS X2 X1 ISDA/P3.4/T0 ISCL/P7.7 VCOAST/P4.2 P6.2/AD2 P1.0 7 8 9 10 11 12 13 14 15 16 17
HSDA2/P7.6
DA0/P5.0 VDD3
DA5/P5.5
3 4 5 6 21 20 19 18 P1.3 P1.2 P3.2/INT0 P1.1
MTV412M 44 Pin PLCC
41 42 43 44 1 2 27 26 25 24 23 22 P1.5 P1.4 P6.0/AD0 P6.1/AD1 P1.7 P1.6
40 39 38 37 36 35 34 33 32 31 30 29 28 HSDA/P3.1/Txd DA8/P7.1 DA9/P7.2 HBLANK/P4.1 VBLANK/P4.0 DA7/P7.0/HCLAMP DA6/P5.6/CKO P6.7/DA13 P6.6/DA12 P6.5/DA11 P6.4/DA10 HSCL/P3.0/Rxd
Revision 0.9
-2-
April 2002
MYSON-CENTURY TECHNOLOGY
PIN CONFIGURATION
MTV412M (Rev 0.9)
A "CMOS output pin" means it can sink and drive at least 4mA current. It is not recommended to use such pin as input function. A "open drain pin" means it can sink at least 4mA current but only drive 10~20uA to VDD. It can be used as input or output function and needs an external pull up resistor. A "8051 standard pin" is a pseudo open drain pin. It can sink at least 4mA current when output is at low level, and drives at least 4mA current for 160nS when output transits from low to high, then keeps driving at 100uA to maintain the pin at high level. It can be used as input or output function. It needs an external pull up resistor when driving heavy load device.
4mA
10uA
120uA
2 OSC period delay 4mA Output Data Input Data
8051 Standard Pin
Pin
4mA No Current
Output Data 4mA
Pin Input Data 4mA Output Data Pin
CMOS Output Pin
Open Drain Pin
POWER CONFIGURATION
The MTV412M can work on 5V or 3.3V power supply system. In 5V power system, the VDD pin is connected to 5V power and the VDD3 needs an external capacitor, all output pins can swing from 0~5V, input pins can accept 0~5V input range. And ADC conversion range is 5V. However, X1 and X2 pins must be kept below 3.3V. In 3.3V power system, the VDD and VDD3 are connected to 3.3V power, all output pins swing from 0~3.3V, HSYNC, VSYNC and open drain pin can accept 0~5V input range, other pins must be kept below 3.3V. And the ADC conversion range is 3.3V.
5V VDD VDD VDD3 VDD3 10u 3.3V VDD VDD3
MTV412M in 5V System
MTV412M in 3.3V System
Revision 0.9
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April 2002
MYSON-CENTURY TECHNOLOGY
PIN DESCRIPTION
Name VDD3 VDD VSS X2 X1 RST DA0/P5.0 DA1/P5.1 DA2/P5.2 DA3/P5.3 DA4/P5.4 DA5/P5.5 DA6/P5.6/CKO DA7/P7.0/HCLAMP DA8/P7.1 DA9/P7.2 HSCL1/P3.0/Rxd HSDA1/P3.1/Txd HSCL2/P7.5 HSDA2/P7.6 P3.2/INT0 ISDA/P3.4/T0 ISCL/P7.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P6.0/AD0 P6.1/AD1 P6.2/AD2 P6.3/AD3 P6.4/DA10 P6.5/DA11 P6.6/DA12 P6.7/DA13 VBLANK/P4.0 HBLANK/P4.1 P4.2 HSYNC/P7.3 VSYNC/P7.4 PIN NO. 42 44 4 4 8 8 9 10 10 11 11 12 7 7 3 3 2 2 1 1 40 42 39 41 38 40 32 33 37 36 28 27 6 5 18 12 13 16 17 19 20 21 22 23 24 26 25 15 29 30 31 34 35 14 41 42 34 35 39 38 29 28 6 5 19 13 14 17 18 20 21 22 23 24 25 27 26 16 9 30 31 32 33 36 37 15 43 44 Type O O I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O I/O I/O Description
MTV412M (Rev 0.9)
3.3V core power 5V or 3.3V Positive Power Supply Ground Oscillator output Oscillator input Active high reset PWM DAC output / General purpose I/O (CMOS) PWM DAC output / General purpose I/O (CMOS) PWM DAC output / General purpose I/O (CMOS) PWM DAC output / General purpose I/O (CMOS) PWM DAC output / General purpose I/O (CMOS) PWM DAC output / General purpose I/O (CMOS) PWM DAC output / General purpose I/O / Oscillator Freq. clock output (CMOS) PWM DAC output / General purpose I/O / Hsync clamp pulse output (CMOS) PWM DAC output / General purpose I/O (open drain) PWM DAC output / General purpose I/O (open drain) Slave IIC 1 clock / General purpose I/O / Rxd (open drain) Slave IIC 1 data / General purpose I/O / Txd (open drain) Slave IIC 2 clock / General purpose I/O (open drain) Slave IIC 2 data / General purpose I/O (open drain) General purpose I/O / INT0 (8051 standard) Master IIC data / General purpose I/O / T0 (open drain) Master IIC clock / General purpose I/O (open drain) General purpose I/O (CMOS output or 8051 standard) General purpose I/O (CMOS output or 8051 standard) General purpose I/O (CMOS output or 8051 standard) General purpose I/O (CMOS output or 8051 standard) General purpose I/O (CMOS output or 8051 standard) General purpose I/O (CMOS output or 8051 standard) General purpose I/O (CMOS output or 8051 standard) General purpose I/O (CMOS output or 8051 standard) General purpose I/O / ADC Input (CMOS) General purpose I/O / ADC Input (CMOS) General purpose I/O / ADC Input / Half Hsync input (CMOS) General purpose I/O / ADC Input (CMOS) General purpose I/O / PWM DAC output (CMOS) General purpose I/O / PWM DAC output (CMOS) General purpose I/O / PWM DAC output (CMOS) General purpose I/O / PWM DAC output (CMOS) Vertical blank (CMOS) / General purpose Output (CMOS) Horizontal blank (CMOS) / General purpose Output (CMOS) General purpose Output (CMOS) Horizontal SYNC or Composite SYNC Input / General purpose I/O (CMOS) Vertical SYNC input / General purpose I/O (CMOS)
Revision 0.9
-4-
April 2002
MYSON-CENTURY TECHNOLOGY
FUNCTIONAL DESCRIPTIONS
1. 8051 CPU Core
MTV412M (Rev 0.9)
The CPU core of MTV412M is compatible with the industry standard 8051, which includes 256 bytes RAM, Special Function Registers (SFR), two timers, five interrupt sources and a serial interface. The CPU core fetches its program code from the 128K bytes Flash in MTV412M. It uses Port0 and Port2 to access the "external special function register" (XFR) and external auxiliary RAM (AUXRAM). The CPU core can run at double rate when FclkE is set. Once the bit is set, the CPU runs as if a 24MHz X'tal is applied on MTV412M, but the peripherals (IIC, DDC, H/V processor) still run at the original frequency. Note: All registers listed in this document reside in 8051's external RAM area (XFR). For internal RAM memory map, please refer to 8051 spec. 2. Memory Allocation 2.1 Internal Special Function Registers (SFR) The SFR is a group of registers that are the same as standard 8051. 2.2 Internal RAM There are total 256 bytes internal RAM in MTV412M, the same as standard 8052. 2.3 External Special Function Registers (XFR) The XFR is a group of registers allocated in the 8051 external RAM area F00h - FFFh. These registers are used for special functions. Programs can use "MOVX" instruction to access these registers. 2.4 Auxiliary RAM (AUXRAM) There are total 256 bytes auxiliary RAM allocated in the 8051 external RAM area 800h - 8FFh. Programs can use "MOVX" instruction to access the AUXRAM. 2.5 Dual Port RAM (DDCRAM1 & DDCRAM2) There are 2x256 bytes Dual Port RAM allocated in the 8051 external RAM area 900h - 9FFh & E00h - EFFh for H/W auto transfer DDC. The external DDC1/2 Host can access the RAM as if two 24LC02 EEPROMs are connected onto the interface. The HSCL1, HSDA1 pins can access DDCRAM1 directly. And the HSCL2, HSDA2 pins can access DDCRAM2 directly. Programs can also use "MOVX" instruction to access these RAM.
FFh
Internal RAM
Accessible by indirect addressing only (Using MOV A,@Ri instruction)
SFR
Accessible by direct addressing
FFFh
XFR
Accessible by indirect external RAM addressing (Using MOVX instruction)
EFFh
DDCRAM1
Accessible by indirect external RAM addressing (Using MOVX instruction)
80h 7Fh
Internal RAM
Accessible by direct and indirect addressing
F00h 8FFh
AUXRAM
Accessible by indirect external RAM addressing (Using MOVX instruction
E00h 9FFh
DDCRAM2
Accessible by indirect external RAM addressing (Using MOVX instruction)
00h
800h
900h
Revision 0.9
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April 2002
MYSON-CENTURY TECHNOLOGY
3. Chip Configuration
MTV412M (Rev 0.9)
The Chip Configuration registers define configuration of the chip and function of the pins. Reg name PADMOD PADMOD PADMOD PADMOD PADMOD PADMOD OPTION PADMOD PADMOD addr F50h(w) F51h(w) F52h(w) F53h(w) F54h(w) F55h(w) F56h(w) F5Eh(w) F5Fh(w) bit7 DA13E HIIC1E P67oe COP17 PWMF P77oe bit6 DA12E P56E IIICE P56oe P66oe COP16 DIV253 P76oe bit5 DA11E P55E HIIC2E P55oe P65oe COP15 FclkE P75oe Bit4 DA10E P54E CKOE P54oe P64oe COP14 P74E P74oe bit3 AD3E P53E HCLPE P53oe P63oe COP13 ENSCL P73E P73oe bit2 AD2E P52E P42E P52oe P62oe COP12 Msel P72E P72oe bit1 AD1E P51E P41E P51oe P61oe COP11 MIICF1 P71E P71oe bit0 AD0E P50E P40E P50oe P60oe COP10 MIICF0 P70E P70oe
PADMOD (w) : Pad mode control registers. (All are "0" in Chip Reset, except for HIIC1E bit) Pin "P6.7/DA13" is DA13. DA13E = 1 Pin "P6.7/DA13" is P6.7. =0 DA12E = 1 Pin "P6.6/DA12" is DA12. =0 Pin "P6.6/DA12" is P6.6. DA11E = 1 Pin "P6.5/DA11" is DA11. Pin "P6.5/DA11" is P6.5. =0 Pin "P6.4/DA10" is DA10. DA10E = 1 Pin "P6.4/DA10" is P6.4. =0 Pin "P6.3/AD3" is AD3. AD3E = 1 Pin "P6.3/AD3" is P6.3. =0 Pin "P6.2/AD2" is AD2. AD2E = 1 Pin "P6.2/AD2" is P6.2. =0 AD1E = 1 Pin "P6.1/AD1" is AD1. =0 Pin "P6.1/AD1" is P6.1. Pin "P6.0/AD0" is AD0. AD0E = 1 Pin "P6.0/AD0" is P6.0. =0 Pin "DA6/P5.6/CKO" is P5.6. P56E = 1 Pin "DA6/P5.6/CKO" is DA6/CKO selected by CKOE bit. =0 Pin "DA5/P5.5" is P5.5. P55E = 1 Pin "DA5/P5.5" is DA5. =0 Pin "DA4/P5.4" is P5.4. P54E = 1 =0 Pin "DA4/P5.4" is DA4. P53E = 1 Pin "DA3/P5.3" is P5.3. =0 Pin "DA3/P5.3" is DA3. Pin "DA2/P5.2" is P5.2. P52E = 1 Pin "DA2/P5.2" is DA2. =0 Pin "DA1/P5.1" is P5.1. P51E = 1 Pin "DA1/P5.1" is DA1. =0 Pin "DA0/P5.0" is P5.0. P50E = 1 Pin "DA0/P5.0" is DA0. =0 Pin "HSCL1/P3.0/Rxd" is HSCL1; HIIC1E = 1 pin "HSDA1/P3.1/Txd" is HSDA1. =0 Pin "HSCL1/P3.0/Rxd" is P3.0/Rxd; pin "HSDA1/P3.1/Txd" is P3.1/Txd. IIICE = 1 Pin "ISDA/P3.4/T0" is ISDA; pin "ISCL/P7.7" is ISCL. Pin "ISDA/P3.4/T0" is P3.4/T0; =0 pin "ISCL/P7.7" is P7.7. Pin "HSCL2/P7.5" is HSCL2. HIIC2E = 1 Pin "HSDA2/P7.6" is HSDA6. Pin "HSCL2/P7.5" is P7.5. =0 Pin "HSDA2/P7.6" is P7.6. Revision 0.9 -6April 2002
MYSON-CENTURY TECHNOLOGY
CKOE = 1 =0 HCLPE = 1 =0 P42E = 1 =0 P41E = 1 =0 P40E = 1 =0 P56oe = 1 =0 P55oe = 1 =0 P54oe = 1 =0 P53oe = 1 =0 P52oe = 1 =0 P51oe = 1 =0 P50oe = 1 =0 P67oe = 1 =0 P66oe = 1 =0 P65oe = 1 =0 P64oe = 1 =0 P63oe = 1 =0 P62oe = 1 =0 P61oe = 1 =0 P60oe = 1 =0 COP17 = 1 =0 COP16 = 1 =0 COP15 = 1 =0 COP14 = 1 =0 COP13 = 1 =0 COP12 = 1 =0 Revision 0.9 Pin "DA6/P5.6/CKO is CKO if P56E = 0. Pin "DA6/P5.6/CKO" is DA6 if P56E = 0. Pin "DA7/P7.0/HCLAMP" is HCLAMP if P70E = 0. Pin "DA7/P7.0/HCLAMP" is DA7 if P70E = 0. Pin "P4.2" is P4.2. Reserved Pin "HBLANK/P4.1" is P4.1. Pin "HBLANK/P4.1" is HBLANK. Pin "VBLANK/P4.0" is P4.0. Pin "VBLANK/P4.0" is VBLANK. P5.6 is output pin. P5.6 is input pin. P5.5 is output pin. P5.5 is input pin. P5.4 is output pin. P5.4 is input pin. P5.3 is output pin. P5.3 is input pin. P5.2 is output pin. P5.2 is input pin. P5.1 is output pin. P5.1 is input pin. P5.0 is output pin. P5.0 is input pin. P6.7 is output pin. P6.7 is input pin. P6.6 is output pin. P6.6 is input pin. P6.5 is output pin. P6.5 is input pin. P6.4 is output pin. P6.4 is input pin. P6.3 is output pin. P6.3 is input pin. P6.2 is output pin. P6.2 is input pin. P6.1 is output pin. P6.1 is input pin. P6.0 is output pin. P6.0 is input pin. Pin "P1.7" is CMOS Output. Pin "P1.7" is 8051 standard I/O. Pin "P1.6" is CMOS Output. Pin "P1.6" is 8051 standard I/O. Pin "P1.5" is CMOS Output. Pin "P1.5" is 8051 standard I/O. Pin "P1.4" is CMOS Output. Pin "P1.4" is 8051 standard I/O. Pin "P1.3" is CMOS Output. Pin "P1.3" is 8051 standard I/O. Pin "P1.2" is CMOS Output. Pin "P1.2" is 8051 standard I/O. -7-
MTV412M (Rev 0.9)
April 2002
MYSON-CENTURY TECHNOLOGY
COP11 = 1 =0 COP10 = 1 =0 P74E = 1 =0 P73E = 1 =0 P72E = 1 =0 P71E = 1 =0 P70E = 1 =0 P77oe = 1 =0 P76oe = 1 =0 P75oe = 1 =0 P74oe = 1 =0 P73oe = 1 =0 P72oe = 1 =0 P71oe = 1 =0 P70oe = 1 =0
MTV412M (Rev 0.9)
Pin "P1.1" is CMOS Output. Pin "P1.1" is 8051 standard I/O. Pin "P1.0" is CMOS Output. Pin "P1.0" is 8051 standard I/O. Pin "VSYNC/P7.4" is P7.4. Pin "VSYNC/P7.4" is VSYNC. Pin "HSYNC/P7.3" is P7.3. Pin "HSYNC/P7.3" is HSYNC. Pin "DA9/P7.2" is P7.2. Pin "DA9/P7.2" is DA9. Pin "DA8/P7.1" is P7.1. Pin "DA8/P7.1" is DA8. Pin "DA7/P7.0/HCLAMP" is P7.0. Pin "DA7/P7.0/HCLAMP" is DA7/HCLAMP selected by HCLPE bit. P7.7 is output pin. P7.7 is input pin. P7.6 is output pin. P7.6 is input pin. P7.5 is output pin. P7.5 is input pin. P7.4 is output pin. P7.4 is input pin. P7.3 is output pin. P7.3 is input pin. P7.2 is output pin. P7.2 is input pin. P7.1 is output pin. P7.1 is input pin. P7.0 is output pin. P7.0 is input pin.
OPTION (w) : Chip option configuration (All are "0" in Chip Reset). Selects 94KHz PWM frequency. PWMF = 1 Selects 47KHz PWM frequency. =0 PWM pulse width is 253-step resolution. DIV253 = 1 =0 PWM pulse width is 256-step resolution. FclkE = 1 CPU is running at double rate CPU is running at normal rate =0 Enable slave IIC block to hold HSCL pin low while MTV412M is unable to ENSCL = 1 catch-up with the external master's speed. Master IIC block connect to HSCL1/HSDA1 pins. Msel = 1 Master IIC block connect to ISCL/ISDA pins. =0 MIICF1,MIICF0 = 1,1 Selects 400KHz Master IIC frequency. = 1,0 Selects 200KHz Master IIC frequency. = 0,1 Selects 50KHz Master IIC frequency. = 0,0 Selects 100KHz Master IIC frequency.
Revision 0.9
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MYSON-CENTURY TECHNOLOGY
4. I/O Ports
MTV412M (Rev 0.9)
4.1 Port1 Port1 is a group of pseudo open drain pins or CMOS output pins. It can be used as general purpose I/O. Behavior of Port1 is the same as standard 8051. 4.2 P3.0-2, P3.4 If these pins are not set as IIC pins, Port3 can be used as general purpose I/O, interrupt, UART and Timer pins. Behavior of Port3 is the same as standard 8051. 4.3 Port4, Port5, Port6 and Port7 Port5, Port6 and Port7 are used as general purpose I/O. S/W needs to set the corresponding P5(n)oe, P6(n)oe and P7(n)oe to define whether these pins are input or output. Port4 is pure output. Reg name PORT5 PORT5 PORT5 PORT5 PORT5 PORT5 PORT5 PORT6 PORT6 PORT6 PORT6 PORT6 PORT6 PORT6 PORT6 PORT4 PORT4 PORT4 PORT7 PORT7 PORT7 PORT7 PORT7 PORT7 PORT7 PORT7 PORT5 (r/w) : PORT6 (r/w) : PORT4 (w) : PORT7 (r/w) : addr F30h(r/w) F31h(r/w) F32h(r/w) F33h(r/w) F34h(r/w) F35h(r/w) F36h(r/w) F38h(r/w) F39h(r/w) F3Ah(r/w) F3Bh(r/w) F3Ch(r/w) F3Dh(r/w) F3Eh(r/w) F3Fh(r/w) F58h(w) F59h(w) F5Ah(w) F70h(r/w) F71h(r/w) F72h(r/w) F73h(r/w) F74h(r/w) F75h(r/w) F76h(r/w) F77h(r/w) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P50 P51 P52 P53 P54 P55 P56 P60 P61 P62 P63 P64 P65 P66 P67 P40 P41 P42 P70 P71 P72 P73 P74 P75 P76 P77
Port 5 data input/output value. Port 6 data input/output value. Port 4 data output value. Port 7 data input/output value.
5. PWM DAC Each output pulse width of PWM DAC converter is controlled by an 8-bit register in XFR. The frequency of Revision 0.9 -9April 2002
MYSON-CENTURY TECHNOLOGY
MTV412M (Rev 0.9)
PWM clock is 47KHz or 94KHz, selected by PWMF. And the total duty cycle step of these DAC outputs is 253 or 256, selected by DIV253. If DIV253=1, writing FDH/FEH/FFH to DAC register generates stable high output. If DIV253=0, the output pulses low at least once even if the DAC register's content is FFH. Writing 00H to DAC register generates stable low output. Reg name DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 DA12 DA13 addr F20h(r/w) F21h(r/w) F22h(r/w) F23h(r/w) F24h(r/w) F25h(r/w) F26h(r/w) F27h(r/w) F28h(r/w) F29h(r/w) F2Ah(r/w) F2Bh(r/w) F2Ch(r/w) F2Dh(r/w) bit7 bit6 bit5 bit4 bit3 bit2 Pulse width of PWM DAC 0 Pulse width of PWM DAC 1 Pulse width of PWM DAC 2 Pulse width of PWM DAC 3 Pulse width of PWM DAC 4 Pulse width of PWM DAC 5 Pulse width of PWM DAC 6 Pulse width of PWM DAC 7 Pulse width of PWM DAC 8 Pulse width of PWM DAC 9 Pulse width of PWM DAC 10 Pulse width of PWM DAC 11 Pulse width of PWM DAC 12 Pulse width of PWM DAC 13 bit1 bit0
DA0-13 (r/w) : The output pulse width control for DA0-13. * All of PWM DAC converters are centered with value 80h after power on. 6. H/V SYNC Processing The H/V SYNC processing block performs the functions of composite signal separation/insertion. SYNC inputs presence check, frequency counting, polarity detection and control, as well as the protection of VBLANK output while VSYNC speeds up in high DDC communication clock rate. Based on the digital filter, the HSYNC present and frequency function block treat any pulse longer than the specified time period as pulse, and the specified time period is controlled by (DF1,DF0) bits. The VSYNC digital filter has no control bit. It works as (DF1,DF0) = (0, 0) of HSYNC.
Revision 0.9
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April 2002
MYSON-CENTURY TECHNOLOGY
Digital Filter Present Check Vpre
MTV412M (Rev 0.9)
Polarity Check & Freq. Count
Vfreq Vpol Vbpl
VSYNC CVSYNC XOR Vself Present Check CVpre XOR VBLANK
Digital Filter
Polarity Check & Sync Seperator Present Check & Freq. Count
Hpol
Hpre Hfreq Hbpl
Composite Pulse Insert XOR HSYNC XOR HBLANK
H/V SYNC Processor Block Diagram
6.1 Composite SYNC separation/insertion The MTV412M continuously monitors the input HSYNC. If the vertical SYNC pulse can be extracted from the input, a CVpre flag is set and users can select the extracted "CVSYNC" for the source of polarity check, frequency count, and VBLANK output. The CVSYNC then has 8us delay compared to the original signal. The MTV412M can also insert pulse to HBLANK output during composite VSYNC's active time. The width of insert pulse is 1/8 HSYNC period and the insertion frequency can adapt to original HSYNC. The insert pulse of HBLANK can be disabled or enabled by setting "NoHins" control bit. If "NoHins" bit is set to "1", HBLANK output will be same as HSYNC input (of course, polarity can be controlled by HBpl bit). 6.2 H/V Frequency Counter MTV412M can discriminate HSYNC/VSYNC frequency and save the information in XFRs. The 14-bit Hcounter counts the time of 64xHSYNC period, then loads the result into the HCNTH/HCNTL latch. The output value is then [(128000000/H-Freq) - 1], updated once per VSYNC/CVSYNC period when VSYNC/CVSYNC is present or continuously updated when VSYNC/CVSYNC is non-present. The 12-bit Vcounter counts the time between two VSYNC pulses, then loads the result into the VCNTH/VCNTL latch. The output value is then (62500/V-Freq), updated every VSYNC/CVSYNC period. An extra overflow bit indicates the condition of H/V counter overflow. The VFchg/HFchg interrupt is set when VCNT/HCNT value changes or overflows. Table 6.2.1 and Table 6.2.2 show the HCNT/VCNT value under the operations of 12MHz.
Revision 0.9
- 11 -
April 2002
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MTV412M (Rev 0.9)
VSYNC
HSYNC H OR V H XOR V Single Serrated Double Serrated + Equal.
EXTRVS for H OR V & Single Serrated
8us
8us
EXTRVS for H XOR V 8us EXTRVS for Double Serrated + Equal. 8us
8us Insert HSYNC pulse
8us
EXTRHS for
H OR V & H XOR V & Single Serrated
1/8 HSYNC period Insert HSYNC pulse
EXTRHS for
Double Serrated + Equal. VCOAST for H OR V & H XOR V & Single Serrated VCOAST for Double Serrated + Equal. 1/8 HSYNC period
1/2 HSYNC period
8us
1/2 HSYNC period
3/4 HSYNC period
Timing Relationship of Composite SYNC signal Separation/Insertion when "NoHins" = 0
Revision 0.9
- 12 -
April 2002
MYSON-CENTURY TECHNOLOGY
6.2.1 H-Freq Table H-Freq(KHZ) 1 2 3 4 5 6 7 8 9 10 11 12 31.5 37.5 43.3 46.9 53.7 60.0 68.7 75.0 80.0 85.9 93.8 106.3 Output Value (14 bits) 12MHz OSC (hex / dec) 0FDEh / 4062 0D54h / 3412 0B8Bh / 2955 0AA8h / 2728 094Fh / 2383 0854h / 2132 0746h / 1862 06AAh / 1706 063Fh / 1599 05D1h / 1489 0554h / 1364 04B3h / 1203
MTV412M (Rev 0.9)
6.2.2 V-Freq Table V-Freq(Hz) 1 2 3 4 5 6 56 60 70 72 75 85 Output value (12bits) 12MHz OSC (hex / dec) 45Ch / 1116 411h / 1041 37Ch / 892 364h / 868 341h / 833 2DFh / 735
6.3 H/V Present Check The Hpresent function checks the input HSYNC pulse, and the Hpre flag is set when HSYNC is over 10KHz or cleared when HSYNC is under 10Hz. The Vpresent function checks the input VSYNC pulse, and the Vpre flag is set when VSYNC is over 40Hz or cleared when VSYNC is under 10Hz. The HPRchg interrupt is set when the Hpre value changes. The VPRchg interrupt is set when the Vpre/CVpre value change. 6.4 H/V Polarity Detect The polarity functions detect the input HSYNC/VSYNC high and low pulse duty cycle. If the high pulse duration is longer than that of the low pulse, the negative polarity is asserted; otherwise, positive polarity is asserted. The HPLchg interrupt is set when the Hpol value changes. The VPLchg interrupt is set when the Vpol value changes. 6.5 Output HBLANK/VBLANK Control and Polarity Adjust The HBLANK is the mux output of HSYNC and composite Hpulse. The VBLANK is the mux output of VSYNC and CVSYNC. The mux selection and output polarity are S/W controllable. The VBLANK output is cut off when VSYNC frequency is over 250Hz. The HBLANK/VBLANK shares the output pin with P4.1/ P4.0. 6.6 VSYNC Coast Pulse Output This output pin define the period of ADC PLL which is needed to disable locking for composite sync. The output polarity of VCOAST are S/W controllable. 6.7 HSYNC Clamp Pulse Output The HCLAMP output is activated by setting "HCLPE" control bit. The leading edge position, pulse width and polarity of HCLAMP are S/W controllable. 6.8 VSYNC Interrupt The MTV412M checks the VSYNC input pulse and generates an interrupt at its leading edge. The VSYNC flag is set each time when MTV412M detects a VSYNC pulse. he flag is cleared by S/W writing a "0". Revision 0.9 - 13 April 2002
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6.9 H/V SYNC Processor Register Reg name HVSTUS HCNTH HCNTL VCNTH VCNTL HVCTR0 HVCTR2 HVCTR3 HVCTR4 INTFLG INTEN addr bit7 bit6 bit5 bit4 bit3 bit2 F40h(r) CVpre Hpol Vpol Hpre Vpre F41h(r) Hovf HF13 HF12 HF11 HF10 F42h(r) HF7 HF6 HF5 HF4 HF3 HF2 F43h(r) Vovf VF11 VF10 F44h(r) VF7 VF6 VF5 VF4 VF3 VF2 F40h(w) C1 C0 NoHins F42h(w) F43h(w) CLPEG CLPPO CLPW2 CLPW1 CLPW0 F44h(w) F48h(r/w) HPRchg VPRchg HPLchg VPLchg HFchg VFchg F49h(w) EHPR EVPR EHPL EVPL EHF EVF
MTV412M (Rev 0.9)
bit1 Hoff HF9 HF1 VF9 VF1 HBpl
bit0 Voff HF8 HF0 VF8 VF0 VBpl
DF1
DF0 Vsync EVsync
HVSTUS (r) : The status of polarity, present and static level for HSYNC and VSYNC. The extracted CVSYNC is present. CVpre = 1 The extracted CVSYNC is not present. =0 Hpol =1 HSYNC input is positive polarity. HSYNC input is negative polarity. =0 Vpol =1 VSYNC (CVSYNC) is positive polarity. VSYNC (CVSYNC) is negative polarity. =0 Hpre = 1 HSYNC input is present. HSYNC input is not present. =0 Vpre = 1 VSYNC input is present. VSYNC input is not present. =0 Hoff* = 1 Off level of HSYNC input is high. Off level of HSYNC input is low. =0 Voff* = 1 Off level of VSYNC input is high. Off level of VSYNC input is low. =0 *Hoff and Voff are valid when Hpre=0 or Vpre=0. HCNTH (r) : H-Freq counter's high bits. H-Freq counter is overflowed, this bit is cleared by H/W when condition removed. Hovf =1 HF13 - HF8 : 6 high bits of H-Freq counter. HCNTL (r) : H-Freq counter's low byte.
VCNTH (r) : V-Freq counter's high bits. Vovf =1 V-Freq counter is overflowed, this bit is cleared by H/W when condition removed. VF11 - 8 : 4 high bits of V-Freq counter. VCNTL (r) : V-Freq counter's low byte.
HVCTR0 (w) : H/V SYNC processor control register 0. C1, C0 = 1,1 Selects CVSYNC as the polarity, freq and VBLANK source. = 1,0 Selects VSYNC as the polarity, freq and VBLANK source. = 0,0 Disables composite function. = 0,1 H/W automatically switches to CVSYNC when CVpre=1 and VSpre=0. NoHins = 1 HBLANK has no insert pulse in composite mode. =0 HBLANK has insert pulse in composite mode. Negative polarity HBLANK output. HBpl = 1 =0 Positive polarity HBLANK output. Revision 0.9 - 14 April 2002
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VBpl =1 =0 Negative polarity VBLANK output. Positive polarity VBLANK output.
MTV412M (Rev 0.9)
HVCTR3 (w) : HSYNC clamp pulse control register. Clamp pulse follows HSYNC leading edge. CLPEG = 1 Clamp pulse follows HSYNC trailing edge. =0 Positive polarity clamp pulse output. CLPPO = 1 Negative polarity clamp pulse output. =0 CLPW2 : CLPW0 : Pulse width of clamp pulse is [(CLPW2:CLPW0) + 1] x 0.167 s for 12MHz X'tal selection. HVCTR4 (w) : DF1, DF0 : = 0,0
= 0,1
= 1,x INTFLG (w) :
The digital filter will treat any HSYNC pulse shorter than one OSC period (83.33ns) as noise, between one and two OSC period (83.33ns to 166.67ns) as unknown region, and longer than two OSC period (166.67ns) as pulse. The digital filter will treat any HSYNC pulse shorter than half OSC period (41.66ns) as noise, between half and one OSC period (41.66ns to 83.33ns) as unknown region, and longer than one OSC period (83.33ns) as pulse. Disable the digital filter for HSYNC.
Interrupt flag. An interrupt event will set its individual flag, and, if the corresponding interrupt enable bit is set, the INT1 source of 8051 core will be driven by a zero level. Software MUST clear this register while serving the interrupt routine. No action. HPRchg= 1 Clears HSYNC presence change flag. =0 No action. VPRchg= 1 =0 Clears VSYNC presence change flag. HPLchg = 1 No action. Clears HSYNC polarity change flag. =0 No action. VPLchg = 1 Clears VSYNC polarity change flag. =0 No action. HFchg = 1 Clears HSYNC frequency change flag. =0 No action. VFchg = 1 Clears VSYNC frequency change flag. =0 Vsync = 1 No action. =0 Clears VSYNC interrupt flag.
INTFLG (r) : Interrupt flag. Indicates a HSYNC presence change. HPRchg= 1 Indicates a VSYNC presence change. VPRchg= 1 HPLchg = 1 Indicates a HSYNC polarity change. VPLchg = 1 Indicates a VSYNC polarity change. Indicates a HSYNC frequency change or counter overflow. HFchg = 1 Indicates a VSYNC frequency change or counter overflow. VFchg = 1 Indicates a VSYNC interrupt. Vsync = 1 INTEN (w) : EHPR EVPR EHPL EVPL EHF Revision 0.9 Interrupt enable. =1 Enables HSYNC presence change interrupt. Enables VSYNC presence change interrupt. =1 Enables HSYNC polarity change interrupt. =1 Enables VSYNC polarity change interrupt. =1 Enables HSYNC frequency change / counter overflow interrupt. =1 - 15 April 2002
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EVF =1 EVsync = 1 7. DDC & IIC Interface 7.1 DDC1/DDC2x Mode, DDCRAM1/DDCRAM2 and SlaveA1/SlaveA2 block
MTV412M (Rev 0.9)
Enables VSYNC frequency change / counter overflow interrupt. Enables VSYNC interrupt.
The MTV412M supports VESA DDC for both D-sub and DVI interfaces through HSCL1/HSDA1 and HSCL2/HSDA2 pins. The HSCL1/HSDA1 pins access DDCRAM1 by SlaveA1, and the HSCL2/HSDA2 pins access DDCRAM2 by SlaveA2. The MTV412M enters DDC1 mode for both DDC channels after Reset. In this mode, VSYNC is used as data clock. The HSCL1/HSCL2 pin should remain at high. The data output to the HSDA1/HSDA2 pin is taken from a shift register in MTV412M. The shift register automatically fetches EDID data from the lower 128 bytes of the Dual Port RAM (DDCRAM1/DDCRAM2), then sends it in 9-bit packet formats inclusive of a null bit (=1) as packet separator. S/W may enable/disable the DDC1 function by setting/clearing the DDC1en control bit. The MTV412M switches to DDC2x mode when it detects a high to low transition on the HSCL1/HSCL2 pin. In this mode, the SlaveA1/SlaveA2 IIC block automatically transmits/receives data to/from the IIC Master. The transmitted/received data is taken-from/saved-to the DDCRAM1/DDCRAM2. In simple words, MTV412M can behaves as two 24LC02 EEPROMs. The only thing S/W needs to do is to write the EDID data to DDCRAM1/DDCRAM2. These slave address of SlaveA1/SlaveA2 block can be chosen by S/W as 5bit, 6-bit or 7-bit. For example, if S/W chooses 5-bit slave address as 10100b, the SlaveA1 IIC block then responds to slave address 10100xxb. The SlaveA1/SlaveA2 can be enabled/disabled by setting/clearing the EnslvA1/EnslvA2 bit. The lower/upper DDCRAM1/DDCRAM2 can/cannot be written by the IIC Master by setting/clearing the EN128w/En256w bit. Besides, if the Only128 control bit is set, the SlaveA1/SlaveA2 only accesses the lower 128 bytes of the DDCRAM1/DDCRAM2. The MTV412M returns to DDC1 mode if HSCL1 is kept high for 128 VSYNC clock period. However, it locks in DDC2B mode if a valid IIC address (1010xxxb) has been detected on HSCL1/HSDA1 buses. The DDC2 flag reflects the current DDC status, S/W may clear it by writing a "0" to it. 7.2 SlaveB Block The SlaveB IIC block is connected to HSDA1 and HSCL1 pins only. This block can receive/transmit data using IIC protocols. S/W may write the SLVBADR register to determine the slave addresses. In receive mode, the block first detects IIC slave address matching the condition then issues a SlvBMI interrupt. The data from HSDA1 is shifted into shift register then written to RCBBUF register when a data byte is received. The first byte loaded is word address (slave address is dropped). This block also generates a RCBI (receives buffer full interrupt) every time when the RCBBUF is loaded. If S/W is not able to read out the RCBBUF in time, the next byte in shift register is not written to RCBBUF and the slave block returns NACK to the master. This feature guarantees the data integrity of communication. The WadrB flag can tell S/W whether the data in RCBBUF is a word address or not. In transmit mode, the block first detects IIC slave address matching the condition, then issues a SlvBMI interrupt. In the meantime, the data pre-stored in the TXBBUF is loaded into shift register, resulting in TXBBUF emptying and generates a TXBI (transmit buffer empty interrupt). S/W should write the TXBBUF a new byte for the next transfer before shift register empties. A failure of this process causes data corrupt. The TXBI occurs every time when shift register reads out the data from TXBBUF. The SlvBMI is cleared by writing "0" to corresponding bit in INTFLG register. The RCBI is cleared by reading out RCBBUF. The TXBI is cleared by writing TXBBUF. *Please refer to the attachments about "Slave IIC Block Timing". 7.3 Master Mode IIC Function Block The master mode IIC block can be connected to the ISDA /ISCL pins or the HSDA1/HSCL1 pins, selected by Msel control bit. Its speed can be selected within the range of 50KHz-400KHz by S/W setting the MIICF1/MIICF0 control bit. The software program can access the external IIC device through this interface. A summary of master IIC access is illustrated as follows. Revision 0.9 - 16 April 2002
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7.3.1. To write IIC Device 1. Write MBUF the Slave Address. 2. Set S bit to Start. 3. After the MTV412M transmits this byte, a MbufI interrupt is triggered. 4. Programs can write MBUF to transfer next byte or set P bit to stop. * Please refer to the attachments about "Master IIC Transmit Timing".
MTV412M (Rev 0.9)
7.3.2. To read IIC Device 1. Write MBUF the Slave Address. 2. Set S bit to Start. 3. After the MTV412M transmits this byte, a MbufI interrupt is triggered. 4. Set or reset the MAckO flag according to the IIC protocol. 5. Read out MBUF the useless byte to continue the data transfer. 6. After the MTV412M receives a new byte, the MbufI interrupt is triggered again. 7. Read MBUF also trigger the next receive operation, but set P bit before read can terminate the operation. * Please refer to the attachments about "Master IIC Receive Timing". Reg name IICCTR IICSTUS INTFLG INTFLG INTEN MBUF DDCCTRA1 SLVA1ADR RCBBUF TXBBUF SLVBADR DDCCTRA2 SLVA2ADR addr F00h (r/w) F01h (r) F03h (r) F03h (w) F04h (w) F05h (r/w) F06h (w) F07h (w) F08h (r) F08h (w) F09h (w) F86h (w) F87h (w) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 DDC2A1 DDC2A2 MAckO P S WadrB SlvRWB SAckIn SLVS MAckIn TXBI RCBI SlvBMI STOPI ReStaI WslvA1I WslvA2I MbufI SlvBMI STOPI ReStaI WslvA1I WslvA2I MbufI ETXBI ERCBI ESlvBMI ESTOPI EReStaI EWSlvA1I EWSlvA2I EMbufI Master IIC receive/transmit data buffer DDC1en En128W En256W Only128 SlvA1bs1 SlvA1bs0 ENSlvA1 Slave A1 IIC address Slave B IIC receive buffer Slave B IIC transmit buffer ENSlvB Slave B IIC address DDC1en En128W En256W Only128 SlvA2bs1 SlvA2bs0 ENSlvA2 Slave A2 IIC address
IICCTR (r/w) : IIC interface status/control register. DDC2 is active for HSCL1/HSDA1 pins. DDC2A1 = 1 MTV412M remains in DDC1 mode for HSCL1/HSDA1 pins. =0 DDC2A2 = 1 DDC2 is active for HSCL2/HSDA2 pins. =0 MTV412M remains in DDC1 mode for HSCL2/HSDA2 pins. In master receive mode, NACK is returned by MTV412M. MAckO = 1 In master receive mode, ACK is returned by MTV412M. =0 S, P = , 0 Start condition when Master IIC is not during transfer. = X, Stop condition when Master IIC is not during transfer. = 1, X Resume transfer after a read/write MBUF operation. IICSTUS (r) : IIC interface status register. The data in RCBBUF is word address. WadrB = 1 Current transfer is slave transmit SlvRWB = 1 Current transfer is slave receive =0 The external IIC host respond NACK. SAckIn = 1 The slave block has detected a START, cleared when STOP detected. SLVS = 1 Master IIC bus error, no ACK received from the slave IIC device. MAckIn = 1 =0 ACK received from the slave IIC device. Revision 0.9 - 17 April 2002
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INTFLG (w) :
MTV412M (Rev 0.9)
Interrupt flag. A interrupt event will set its individual flag, and, if the corresponding interrupt enable bit is set, the 8051 INT1 source will be driven by a zero level. Software MUST clear this register while serving the interrupt routine. No action. SlvBMI = 1 Clears SlvBMI flag. =0 No action. STOPI = 1 =0 Clears STOPI flag. ReStaI = 1 No action. Clears ReStaI flag. =0 No action. WslvA1I = 1 Clears WslvA1I flag. =0 No action. WslvA2I = 1 Clears WslvA2I flag. =0 No action. MbufI = 1 Clears Master IIC bus interrupt flag (MbufI). =0
INTFLG (r) : TXBI RCBI
Interrupt flag. Indicates the TXBBUF need a new data byte, cleared by writing TXBBUF. =1 Indicates the RCBBUF has received a new data byte, cleared by reading =1 RCBBUF. SlvBMI = 1 Indicates the slave IIC address B match condition. STOPI = 1 Indicates the slave IIC has detected a STOP condition for HSCL1/HSDA1 pins. Indicates the slave IIC has detected a repeat START condition for HSCL1/HSDA1 ReStaI = 1 pins. Indicates the slave A1 IIC has detected a STOP condition of write mode. WslvA1I = 1 Indicates the slave A2 IIC has detected a STOP condition of write mode. WslvA2I = 1 Indicates a byte is sent/received to/from the master IIC bus. MbufI = 1
INTEN (w) : Interrupt enable. Enables TXBBUF interrupt. ETXBI = 1 Enables RCBBUF interrupt. ERCBI = 1 Enables slave address B match interrupt. ESlvBMI = 1 Enables IIC bus STOP interrupt. ESTOPI = 1 EReStaI = 1 Enables IIC bus repeat START interrupt. EWSlvA1I = 1 Enables slave A1 IIC bus STOP of write mode interrupt. EWSlvA2I = 1 Enables slave A2 IIC bus STOP of write mode interrupt. Enables Master IIC bus interrupt. EMbufI = 1 Mbuf (w) : Master IIC data shift register, after START and before STOP condition, write this register resumes MTV412M's transmission to the IIC bus. Master IIC data shift register, after START and before STOP condition, read this register resumes MTV412M's reception from the IIC bus.
Mbuf (r) :
DDCCTRA1 (w) : DDC interface control register for HSCL1, HSDA1 pins. Enables DDC1 data transfer in DDC1 mode. DDC1en = 1 Disables DDC1 data transfer in DDC1 mode. =0 The lower 128 bytes (00-7F) of DDCRAM1 can be written by IIC master. En128W = 1 =0 The lower 128 bytes (00-7F) of DDCRAM1 cannot be written by IIC master. En256W = 1 The higher 128 bytes (80-FF) of DDCRAM1 can be written by IIC master. The higher 128 bytes (80-FF) of DDCRAM1 cannot be written by IIC master. =0 The SlaveA1 always accesses EDID data from the lower 128 bytes of DDCRAM1. Only128 = 1 The SlaveA1 accesses EDID data from the whole 256 bytes DDCRAM1. =0 SlvA1bs1,SlvA1bs0 : Slave IIC block A1's slave address length. Revision 0.9 - 18 April 2002
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= 1,0 = 0,1 = 0,0 5-bit slave address. 6-bit slave address. 7-bit slave address.
MTV412M (Rev 0.9)
SLVA1ADR (w) : Slave IIC block A1's enable and address. Enables slave IIC block A1. EnslvA1= 1 Disables slave IIC block A1. =0 bit6-0 : Slave IIC address A1 to which the slave block should respond. RCBBUF (r) : Slave IIC block B receives data buffer.
TXBBUF (w) : Slave IIC block B transmits data buffer. SLVBADR (w) : Slave IIC block B's enable and address. ENslvB = 1 Enables slave IIC block B. =0 Disables slave IIC block B. bit6-0 : Slave IIC address B to which the slave block should respond. DDCCTRA2 (w) : DDC interface control register for HSCL2, HSDA2 pins. DDC1en = 1 Enables DDC1 data transfer in DDC1 mode. =0 Disables DDC1 data transfer in DDC1 mode. The lower 128 bytes (00-7F) of DDCRAM2 can be written by IIC master. En128W = 1 The lower 128 bytes (00-7F) of DDCRAM2 cannot be written by IIC master. =0 The higher 128 bytes (80-FF) of DDCRAM2 can be written by IIC master. En256W = 1 The higher 128 bytes (80-FF) of DDCRAM2 cannot be written by IIC master. =0 The SlaveA2 always accesses EDID data from the lower 128 bytes of DDCRAM2. Only128 = 1 The SlaveA2 accesses EDID data from the whole 256 bytes DDCRAM2. =0 SlvA2bs1,SlvA2bs0 : Slave IIC block A2's slave address length. = 1,0 5-bit slave address. = 0,1 6-bit slave address. = 0,0 7-bit slave address. SLVA2ADR (w) : Slave IIC block A2's enable and address. EnslvA2= 1 Enables slave IIC block A2. =0 Disables slave IIC block A2. bit6-0 : Slave IIC address A2 to which the slave block should respond. 8. Low Power Reset (LVR) & Watchdog Timer When the voltage level of power supply is below 3.8V(+/-0.2V) / 2.5V(+/-0.15V) in 5V / 3.3V applications for a specific period of time, the LVR generates a chip reset signal. After the power supply is above 3.8V(+/0.2V) / 2.5V(+/-0.15V) in 5V / 3.3V applications, LVR maintains in reset state for 144 X'tal cycle to guarantee the chip exit reset condition with a stable X'tal oscillation. The Watchdog Timer automatically generates a device reset when it is overflowed. The interval of overflow is 0.25 sec x N, where N is a number from 1 to 8, and can be programmed via register WDT(2:0). The timer function is disabled after power on reset, users can activate this function by setting WEN, and clear the timer by setting WCLR. 9. A/D converter The MTV312M is equipped with four VDD range 8-bit A/D converters. So if the VDD = 5V/3.3V, and then the ADC conversion range is 5V/3.3V, S/W can select the current convert channel by setting the SADC1/SADC0 bit. The refresh rate for the ADC is OSC freq./1536 (128us for 12MHz X'tal). Revision 0.9 - 19 April 2002
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MTV412M (Rev 0.9)
The ADC compares the input pin voltage with internal VDD*N/64 voltage (where N = 0 - 255). The ADC output value is N when pin voltage is greater than VDD*N/255 and smaller than VDD*(N+1)/255. Reg name addr bit7 bit6 bit5 bit4 bit3 bit2 ADC F10h (w) ENADC SADC3 SADC2 ADC F10h (r) ADC convert result WDT F18h (w) WEN WCLR WDT2 WDT (w) : Watchdog Timer control register. Enables Watchdog Timer. WEN =1 WCLR =1 Clears Watchdog Timer. WDT2: WDT0 = 0 Overflow interval = 8 x 0.25 sec. Overflow interval = 1 x 0.25 sec. =1 Overflow interval = 2 x 0.25 sec. =2 Overflow interval = 3 x 0.25 sec. =3 Overflow interval = 4 x 0.25 sec. =4 Overflow interval = 5 x 0.25 sec. =5 Overflow interval = 6 x 0.25 sec. =6 Overflow interval = 7 x 0.25 sec. =7 ADC (w) : ADC control. ENADC =1 SADC0 =1 SADC1 =1 SADC2 =1 SADC3 =1 ADC (r) : Enables ADC. Selects ADC0 pin input. Selects ADC1 pin input. Selects ADC2 pin input. Selects ADC3 pin input. bit1 SADC1 WDT1 bit0 SADC0 WDT0
ADC convert result.
11. In System Programming function (ISP) The Flash memory can be programmed by a specific WRITER in parallel mode, or by IIC Host in serial mode while the system is working. The features of ISP are outlined as below: 1. 2. 3. 4. 5. 6. 7. 8. 9. Single 3.3V power supply for Program/Erase/Verify. Block Erase: 1024 bytes for Program Code, 10mS Whole Flash erase (Blank): 10mS Byte/Word programming Cycle time: 60uS per byte Read access time: 50ns Only one two-pin IIC bus (shared with DDC2) is needed for ISP in user/factory mode. IIC Bus clock rates up to 140KHz. Whole 128K-byte Flash programming within 12 Sec. CRC check provides 100% coverage for all single/double bit errors.
There are two methods to enter the ISP mode which are described as below: Method 1). The Valid ISP Slave Address and Compared data are transmitted Method 2). Write 93h to ISP enable register (ISPEN) Reg name ISPSLV ISPEN addr F0Bh(w) F0Ch(w) bit7 bit6 bit5 bit4 bit3 bit2 ISP Slave address Write 93h to enable ISP Mode bit1 bit0
ISPSLV (w) : ISP Slave IIC's address. bit7-2 : ISP Slave IIC's address to which the ISP block should respond. The default value is 100101. ISPEN(w) : Write 93h to enable ISP Mode for ISP enable method 2. Revision 0.9 - 20 April 2002
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Memory Map of XFR
Reg name addr IICCTR F00h (r/w) IICSTUS F01h (r) INTFLG F03h (r) INTFLG F03h (w) INTEN F04h (w) MBUF F05h (r/w) DDCCTR F06h (w) SLVAADR F07h (w) RCBBUF F08h (r) TXBBUF F08h (w) SLVBADR F09h (w) ISPSLV F0Bh(w) ISPEN F0Ch(w) ISPCMP1 F0Dh(w) ISPCMP2 F0Eh(w) ISPCMP3 F0Fh(w) ADC F10h (w) ADC F10h (r) WDT F18h (w) DA0 F20h(r/w) DA1 F21h(r/w) DA2 F22h(r/w) DA3 F23h(r/w) DA4 F24h(r/w) DA5 F25h(r/w) DA6 F26h(r/w) DA7 F27h(r/w) DA8 F28h(r/w) DA9 F29h(r/w) DA10 F2Ah(r/w) DA11 F2Bh(r/w) DA12 F2Ch(r/w) DA13 F2Dh(r/w) PORT5 F30h(r/w) PORT5 F31h(r/w) PORT5 F32h(r/w) PORT5 F33h(r/w) PORT5 F34h(r/w) PORT5 F35h(r/w) PORT5 F36h(r/w) PORT6 F38h(r/w) PORT6 F39h(r/w) PORT6 F3Ah(r/w) PORT6 F3Bh(r/w) PORT6 F3Ch(r/w) PORT6 F3Dh(r/w) PORT6 F3Eh(r/w) PORT6 F3Fh(r/w) HVSTUS F40h(r) HCNTH F41h(r) Revision 0.9 bit7 DDC2 WadrB TXBI ETXBI DDC1en ENSlvA bit6 bit5 bit4 bit3 bit2 MAckO
MTV412M (Rev 0.9)
bit1 P
ENSlvB
ENADC WEN
CVpre Hovf
SlvRWB SAckIn SLVS SlvBMI STOPI ReStaI WSlvAI SlvBMI STOPI ReStaI WSlvAI ERCBI ESlvBMI ESTOPI EReStaI EWSlvAI Master IIC receives/transmits data buffer En128W En256W Only128 SlvAbs1 SlvAbs0 Slave A IIC address Slave B IIC receives buffer Slave B IIC transmits buffer Slave B IIC address ISP Slave address Write 93h to enable ISP Mode ISP compared data 1 [7:0] ISP compared data 2 [7:0] ISP compared data 3 [7:0] SADC3 SADC2 SADC1 SADC0 ADC convert Result WCLR WDT2 WDT1 WDT0 Pulse width of PWM DAC 0 Pulse width of PWM DAC 1 Pulse width of PWM DAC 2 Pulse width of PWM DAC 3 Pulse width of PWM DAC 4 Pulse width of PWM DAC 5 Pulse width of PWM DAC 6 Pulse width of PWM DAC 7 Pulse width of PWM DAC 8 Pulse width of PWM DAC 9 Pulse width of PWM DAC 10 Pulse width of PWM DAC 11 Pulse width of PWM DAC 12 Pulse width of PWM DAC 13 P50 P51 P52 P53 P54 P55 P56 P60 P61 P62 P63 P64 P65 P66 P67 Hpol Vpol Hpre Vpre Hoff Voff HF13 HF12 HF11 HF10 HF9 HF8 - 21 April 2002 RCBI
bit0 S MAckIn MbufI MbufI EMbufI
MYSON-CENTURY TECHNOLOGY
HCNTL VCNTH VCNTL HVCTR0 HVCTR3 HVCTR4 INTFLG INTEN PADMOD PADMOD PADMOD PADMOD PADMOD PADMOD OPTION PORT4 PORT4 PORT4 PADMOD PADMOD PORT7 PORT7 PORT7 PORT7 PORT7 PORT7 PORT7 PORT7 EPADRH EPADRL EPDATA INTFLG INTEN F42h(r) F43h(r) F44h(r) F40h(w) F43h(w) F44h(w) F48h(r/w) F49h(w) F50h(w) F51h(w) F52h(w) F53h(w) F54h(w) F55h(w) F56h(w) F58h(w) F59h(w) F5Ah(w) F5Eh(w) F5Fh(w) F70h(r/w) F71h(r/w) F72h(r/w) F73h(r/w) F74h(r/w) F75h(r/w) F76h(r/w) F77h(r/w) FF1h(w) FF2h(w) FF3h(r/w) FF4h(r/w) FF5h(w) HF7 Vovf VF7 C1 HF6 VF6 C0 CLPEG HF5 HF4 VF5 VF4 NoHins CLPPO CLPW2 CLPW1 CLPW0 HFchg EHF AD3E P53E HCLPE P53oe P63oe COP13 ENSCL VFchg EVF AD2E P52E P42E P52oe P62oe COP12 Msel HF3 VF11 VF3 HF2 VF10 VF2
MTV412M (Rev 0.9)
HF1 VF9 VF1 HBpl DF1 HF0 VF8 VF0 VBpl DF0 Vsync EVsync AD0E P50E P40E P50oe P60oe COP10 MIICF0 P40 P41 P42 P70E P70oe P70 P71 P72 P73 P74 P75 P76 P77 EADR8 EADR0 EPbpf EEPbpf
VCpol HPRchg VPRchg HPLchg VPLchg EHPR EVPR EHPL EVPL DA13E DA12E DA11E DA10E P56E P55E P54E HIIC1E IIICE HIIC2E CKOE P56oe P55oe P54oe P67oe P66oe P65oe P64oe COP17 COP16 COP15 COP14 PWMF DIV253 FclkE
AD1E P51E P41E P51oe P61oe COP11 MIICF1
P77oe
P76oe
P75oe
P74E P74oe
P73E P73oe
P72E P72oe
P71E P71oe
EADR7
EADR6
EADR5
EADR4 EADR3 EDATA [7:0]
EADR10 EADR9 EADR2 EADR1
Revision 0.9
- 22 -
April 2002
MYSON-CENTURY TECHNOLOGY
ELECTRICAL PARAMETERS
1. Absolute Maximum Ratings at: Ta= 0 to 70 oC, VSS=0V Name Maximum Supply Voltage Maximum Input Voltage (HSYNC, VSYNC & open-drain pins) Maximum Input Voltage (other pins) Maximum Output Voltage Maximum Operating Temperature Maximum Storage Temperature
MTV412M (Rev 0.9)
Symbol VDD Vin1 Vin2 Vout Topg Tstg
Range -0.3 to +6.0 -0.3 to 5V+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 0 to +70 -25 to +125
Unit V V V V oC oC
2. Allowable Operating Conditions at: Ta= 0 to 70 oC, VSS=0V Name Symbol Supply Voltage Input "H" Voltage Input "L" Voltage Operating Freq. VDD Vih1 Vih2 Vil1 Vil2 Fopg
Condition 5V applications 3.3V applications 5V applications 3.3V applications 5V applications 3.3V applications
Min. 4.5 3.0 0.4 x VDD 0.6 x VDD -0.3 -0.3 -
Max. 5.5 3.6 VDD +0.3 VDD +0.3 0.2 x VDD 0.3 x VDD 15
Unit V V V V V V MHz
3. DC Characteristics at: Ta=0 to 70 oC, VDD=5.0V/3.3V, VSS=0V Name Symbol Voh1 Output "H" Voltage, open drain pin Voh2 Voh3 Output "H" Voltage, 8051 I/O port pin Voh4 Voh5 Output "H" Voltage, CMOS output Voh6 Output "L" Voltage Vol Power Supply Current RST Pull-Down Resistor Pin Capacitance Idd Rrst Cio
Condition VDD=5V, Ioh=0uA VDD=3.3V, Ioh=0uA VDD=5V, Ioh=-50uA VDD=3.3V, Ioh=-50uA VDD=5V, Ioh=-4mA VDD=3.3V, Ioh=-4mA Iol=5mA Active Idle Power-Down VDD=5V
Min. 4 2.65 4 2.65 4 2.65
Typ.
Max.
18 1.3 50 150
0.45 24 4.0 80 250 15
Unit V V V V V V V mA mA uA Kohm pF
Revision 0.9
- 23 -
April 2002
MYSON-CENTURY TECHNOLOGY
4. AC Characteristics at: Ta=0 to 70 oC, VDD=5.0V/3.3V, VSS=0V Name Symbol Crystal Frequency fXtal PWM DAC Frequency fDA HS input pulse Width tHIPW VS input pulse Width tVIPW HSYNC to Hblank output jitter tHHBJ H+V to Vblank output delay tVVBD VS pulse width in H+V signal tVCPW
MTV412M (Rev 0.9)
Condition fXtal=12MHz fXtal=12MHz fXtal=12MHz fXtal=12MHz FXtal=12MHz
Min. 46.875 0.3 3
Typ. 12
Max. 94.86 7.5 5
8 20
Unit MHz KHz uS uS nS uS uS
Test Mode Condition
In normal application, users should avoid the MTV412M entering its test mode or writer mode, outlined as follows, adding pull-up resistor to DA8 and DA9 pins is recommended. Test Mode A: RESET=1 & DA9=1 & DA8=0 & P4.2=0 Test Mode B: RESET's falling edge & DA9=1 & DA8=0 & P4.2=1 Writer Mode: RESET=1 & DA9=0 & DA8=1
Revision 0.9
- 24 -
April 2002
MYSON-CENTURY TECHNOLOGY
PACKAGE DIMENSION
1. 42 pin SDIP Unit: mm Symbol A A1 B1 D E1 F eB
MTV412M (Rev 0.9)
Dimension in mm
Min Nom 3.937 4.064 1.78 1.842 0.914 1.270 36.78 36.83 13.945 13.970 15.19 15.240 15.24 16.510 0 7.5
Max 4.2 1.88 1.118 36.88 13.995 15.29 17.78 15
15.494mm +/0.254 13.868mm +/0.102
0.254m m +/-0.102
5o~7
0
6o +/o 16.256mm +/- 3 0.508
2. 44 pin PLCC Unit:
0.045*45 0 PIN #1 HOLE 0.180 MAX. 0.020 MIN.
0.013~0.021 TYP.
0.690 +/-0.005 0.610 +/-0.02 0.653 +/-0.003 0.500
70TYP. 0.010 0.050 TYP. 0.026~0.032 TYP. 0.070 0.653 +/-0.003 0.690 +/-0.005 0.070
Revision 0.9
- 25 -
April 2002
MYSON-CENTURY TECHNOLOGY
Ordering Information
Standard Configurations: Prefix Part Type MTV 412M Package Type S: SDIP V: PLCC F: PQFP ROM Size (K) 128
MTV412M (Rev 0.9)
Revision 0.9
- 26 -
April 2002

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